1. Field Of The Invention
This invention relates to integrated electronic circuit interconnect technology. More particularly, this invention relates to electrically-programmable antifuse elements positioned between two conductive interconnect layers in a programmable interconnect architecture and to processes for fabricating them.
2. The Prior Art
Integrated electronic circuits are usually fabricated with all internal connections set during the manufacturing process. However, because of high development costs and high manufacturing tooling costs of such circuits, circuits have been developed which can be configured or programmed by the user for a specific application by implementing user-programmable interconnect elements. Such circuits are called programmable circuits and may be programmed by using a plurality of programmable interconnect elements which may be either selectively open circuited or short circuited by the end user to create or break circuit connections.
Programmable interconnect elements are programmable electrical interconnect devices which are supplied as connections which may be selectively broken or supplied as open circuits which may be selectively shorted at selected electronic nodes in the circuit by the user after the integrated circuit device has been fabricated, packaged, and supplied to the user. Such programming is undertaken in order to deactivate or activate, respectively, the selected electronic nodes such that the circuit can be programmed to perform a desired function.
Antifuse programmable interconnect elements, supplied as initially open-circuit elements which may be selectively short circuited by programming, have been utilized for customization of integrated circuits such as field programmable gate array integrated circuits. Examples of antifuse structures have been described in the prior art, such as in U.S. Pat. Nos. 4,823,181 and 4,899,205, and in co-pending U.S. patent applications Ser. Nos. 07/508,303 now U.S. Pat. No. 5,050,745 and 07/508,306 07/604,779, now U.S. Pat. No. 5,181,096.
Methods for fabricating antifuses associated with metal layers in a semiconductor structure are known. Antifuses for selectively making connections between regions in a semiconductor substrate and conductive layers disposed above the substrate have been described, for example, in U.S. Pat. Nos. 4,442,507, 4,590,589, 4,424,579, and 4,598,386.
European Patent Application Number 90309731.9, Publication Number 0 416 903 A2 discloses a basic process for forming a metal-to-metal antifuse employing an amorphous silicon antifuse material in which antifuse cell openings are formed simultaneously with the formation of inter-metal vias. The antifuse formed by this process is susceptible to several problems as a result of the fabrication process used to manufacture it. A similar process is described in U.S. Pat. No. 4,458,297, directed to a user-programmable interconnect wiring scheme for hybrid integrated circuit assemblies.
In addition, U.S. Pat. No. 4,914,055 describes a process for fabricating an antifuse associated with an extra metal layer in a double-metal interconnect process. This patent teaches locating the antifuse between the extra metal layer and the first level interconnect rather than between the two levels of interconnect. The process described by this patent requires seven separate photolithographic masking steps to define the antifuse structure.
It would be desirable to develop processes for fabricating a metal-to-metal antifuse which employ a minimum number of masking steps and/or which avoid the problems inherent in the prior art metal-to-metal antifuse fabrication processes.
It is therefore a object of the present invention to develop a process for fabricating a metal-to-metal antifuse which is compatible with a wider variety of via plug technologies.
It is another object of the present invention to develop a process for fabricating a metal-to-metal antifuse which avoids stressing the antifuse material layer around the periphery of the antifuse cell opening.
Yet another object of the present invention is to develop a process for fabricating a metal-to-metal antifuse which produces an antifuse having better controlled breakdown characteristics.
A further object of the present invention is to develop a process for fabricating a metal-to-metal antifuse which is compatible with sputter-deposited antifuse material layer materials.
Another object of the present invention is to develop a process for fabricating a metal-to-metal antifuse which is less susceptible to problems caused by backsputtering steps performed prior to deposition of second layer metal.
An additional object of the present invention is to develop a metal-to-metal antifuse which may be fabricated using a minimum number of photolithography steps.
Yet another object of the present invention is to provide a metal-to-metal antifuse which is located between the two levels of metal normally used for interconnect in a double metal process, or between the second and third levels of metal normally used for interconnect in a triple metal process.
Finally, another object of the present invention is to provide a metal-to-metal antifuse having reduced capacitance whose size is limited by the minimum widths of the two levels of metal interconnect between which it is disposed.
These, and other objects of the present invention will become apparent from the disclosure, drawings, and claims herein.